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"7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs ..."

Yen-Po Lin et al. (2024)

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DOI: 10.1109/ISSCC49657.2024.10454418

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-19

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Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh:
7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS. ISSCC 2024: 136-138

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