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"A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in ..."
Hyung-Jin Lee et al. (2011)
- Hyung-Jin Lee, Alexandra M. Kern, Sami Hyvonen, Ian A. Young:
A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS. ISSCC 2011: 96-97
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