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"A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with ..."

Jahoon Jin et al. (2023)

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DOI: 10.1109/ISSCC42615.2023.10067738

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  dblp key:
  - conf/isscc/JinLMJLCKHJKLK23
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  - https://dblp.org/rec/conf/isscc/JinLMJLCKHJKLK23
Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim:
A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization. ISSCC 2023: 404-405

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