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"An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of ..."

Sander Gierkink (2008)

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DOI: 10.1109/ISSCC.2008.4523253

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Sander Gierkink:
An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL. ISSCC 2008: 454-455

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