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"4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point ..."

Michael Gautschi et al. (2016)

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DOI: 10.1109/ISSCC.2016.7417917

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

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Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster. ISSCC 2016: 82-83

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