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"34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 ..."

Hidehiro Fujiwara et al. (2024)

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DOI: 10.1109/ISSCC49657.2024.10454556

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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  dblp key:
  - conf/isscc/FujiwaraMZKLPJCHHNTLLLCAAWCCLC24
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/FujiwaraMZKLPJCHHNTLLLCAAWCCLC24
Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm² and 3.78Mb/mm² Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. ISSCC 2024: 572-574

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