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"A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and ..."

Hidehiro Fujiwara et al. (2019)

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DOI: 10.1109/ISSCC.2019.8662415

access: closed

type: Conference or Workshop Paper

metadata version: 2019-03-12

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Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin, Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang:
A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. ISSCC 2019: 390-392

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