"A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS ..."

Shaishav Desai, Pradeep Trivedi, Vincent Von Kanael (2007)

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DOI: 10.1109/ISSCC.2007.373417

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Shaishav Desai, Pradeep Trivedi, Vincent Von Kanael:
A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process. ISSCC 2007: 308-605

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