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"7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor."

John Davis et al. (2013)

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DOI: 10.1109/ISSCC.2013.6487754

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-19

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  - https://dblp.org/rec/conf/isscc/DavisBHCSRPKW13
John Davis, Paul Bunce, Diana M. Henderson, Yuen H. Chan, Uma Srinivasan, Daniel Rodko, Pradip Patel, Thomas J. Knips, Tobias Werner:
7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor. ISSCC 2013: 324-325

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