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"Circuit design perspectives for Ge FinFET at 10nm and beyond."
Saurabh Sinha et al. (2015)
- Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov:
Circuit design perspectives for Ge FinFET at 10nm and beyond. ISQED 2015: 57-60
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