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ORCID"Transaction Level Error Susceptibility Model for Bus Based SoC Architectures."
Ing-Chao Lin et al. (2006)
- Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada:
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780
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