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"A methodology to analyze power, voltage drop and their effects on clock ..."

Masato Iwabuchi et al. (1999)

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DOI: 10.1145/299996.300007

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/ispd/IwabuchiSSO99
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Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, Takashi Omachi:
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design. ISPD 1999: 9-15

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