"A real-time silicon cerebellum spiking neural model based on FPGA."

Junwen Luo et al. (2014)

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DOI: 10.1109/ISICIR.2014.7029586

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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Junwen Luo, Graeme Coapes, Patrick Degenaar, Tadashi Yamazaki, Terrence S. T. Mak, Chung Tin:
A real-time silicon cerebellum spiking neural model based on FPGA. ISIC 2014: 276-279

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