"Timing challenges in high-speed interleaved ΔΣ DACs."

Ameya Bhide, Atila Alvandpour (2014)

Details and statistics

DOI: 10.1109/ISICIR.2014.7029513

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-19

a service of  Schloss Dagstuhl - Leibniz Center for Informatics