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"Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for ..."

B. Jhnanesh Somayaji, M. S. Bhat (2016)

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DOI: 10.1109/ISED.2016.7977057

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-01

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B. Jhnanesh Somayaji, M. S. Bhat:
Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications. ISED 2016: 72-76

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