Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Design of STR level converters for SoCs using the multi-island dual-VDD ..."

Jinn-Shyan Wang et al. (2006)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2006.1692999

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/WangCYC06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/WangCYC06
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu:
Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS 2006

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.