![](https://dblp.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
default search action
"A high-voltage DC bias architecture implementation in a 17 Gbps low-power ..."
László Szilágyi et al. (2015)
- László Szilágyi, Guido Belfiore, Ronny Henker, Frank Ellinger:
A high-voltage DC bias architecture implementation in a 17 Gbps low-power common-cathode VCSEL driver in 80 nm CMOS. ISCAS 2015: 2385-2388
![](https://dblp.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.