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"3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS."

Mukesh Kumar Srivastav et al. (2022)

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DOI: 10.1109/ISCAS48785.2022.9937582

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-17

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  - conf/iscas/SrivastavRMGDR22
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  - https://dblp.org/rec/conf/iscas/SrivastavRMGDR22
Mukesh Kumar Srivastav, Rimjhim, Roshan Mishra, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat:
3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS. ISCAS 2022: 1546-1550

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