"Improving FPGA-based Async-logic AES Accelerator with the Integration of ..."

Jun-Sheng Ng et al. (2023)

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DOI: 10.1109/ISCAS46773.2023.10181344

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-19

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Jun-Sheng Ng, Juncheng Chen, Si Wu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee:
Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs. ISCAS 2023: 1-5

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