Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A fast chip-scale power estimation method for large and complex LSIs based ..."

Yuichi Nakamura, Takeshi Yoshimura (2005)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2005.1464666

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-10

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/NakamuraY05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/NakamuraY05
Yuichi Nakamura, Takeshi Yoshimura:
A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis. ISCAS (1) 2005: 628-631

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.