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"A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS ..."

Amandeep Kaur, Deepak Mishra, Mukul Sarkar (2018)

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DOI: 10.1109/ISCAS.2018.8350899

access: closed

type: Conference or Workshop Paper

metadata version: 2021-02-26

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Amandeep Kaur, Deepak Mishra, Mukul Sarkar:
A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors. ISCAS 2018: 1-5

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