"Replica bias scheme for efficient power utilization in high-frequency CMOS ..."

Saravanan Kathiah, Sankaran Aniruddhan (2014)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2014.6865307

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/KathiahA14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/KathiahA14
Saravanan Kathiah, Sankaran Aniruddhan:
Replica bias scheme for efficient power utilization in high-frequency CMOS digital circuits. ISCAS 2014: 1002-1005

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.