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"VLSI Architecture of High Speed SAD for High Efficiency Video Coding ..."

Amit Mahesh Joshi, Mohammad Samar Ansari, Chitrakant Sahu (2018)

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DOI: 10.1109/ISCAS.2018.8351271

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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Amit Mahesh Joshi, Mohammad Samar Ansari, Chitrakant Sahu:
VLSI Architecture of High Speed SAD for High Efficiency Video Coding (HEVC) Encoder. ISCAS 2018: 1-4

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