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"An interconnect optimized floorplanning of a scalar product macrocell."

Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo (2002)

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DOI: 10.1109/ISCAS.2002.1009878

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-25

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  - conf/iscas/GuCY02
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Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo:
An interconnect optimized floorplanning of a scalar product macrocell. ISCAS (1) 2002: 465-468

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