"Design of highly linear multipliers using floating gate transistors and/or ..."

Sri Raga Sudha Garimella et al. (2008)

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DOI: 10.1109/ISCAS.2008.4541712

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-19

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Sri Raga Sudha Garimella, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal:
Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor. ISCAS 2008: 1492-1495

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