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"High speed VLSI architecture design for block turbo decoder."

Zhipei Chi, Keshab K. Parhi (2002)

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DOI: 10.1109/ISCAS.2002.1009987

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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Zhipei Chi, Keshab K. Parhi:
High speed VLSI architecture design for block turbo decoder. ISCAS (1) 2002: 901-904

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