Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear ..."

Yihang Cheng et al. (2023)

> Home

Details and statistics

DOI: 10.1109/ISCAS46773.2023.10181839

access: closed

type: Conference or Workshop Paper

metadata version: 2023-12-27

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/ChengWLZ023
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/ChengWLZ023
Yihang Cheng, Yaning Wang, Fule Li, Chun Zhang, Zhihua Wang:
High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation. ISCAS 2023: 1-5

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.