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"Self-sampled vernier delay line for built-in clock jitter measurement."

Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang (2006)

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DOI: 10.1109/ISCAS.2006.1692904

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/iscas/ChengHJ06
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  - https://dblp.org/rec/conf/iscas/ChengHJ06
Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang:
Self-sampled vernier delay line for built-in clock jitter measurement. ISCAS 2006

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