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ORCID"A mixed PLL/DLL architecture for low jitter clock generation."
Yong-Cheol Bae, Gu-Yeon Wei (2004)
- Yong-Cheol Bae, Gu-Yeon Wei:
A mixed PLL/DLL architecture for low jitter clock generation. ISCAS (4) 2004: 788-791
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