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"Low-leakage power-rail ESD clamp circuit with gated current mirror in a ..."
Federico A. Altolaguirre, Ming-Dou Ker (2013)
- Federico A. Altolaguirre, Ming-Dou Ker:
Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology. ISCAS 2013: 2638-2641
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