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"A 53-61GHz Low-Power PLL With Harmonic Positive Feedback VCO in 65nm CMOS."

Razieh Abedi et al. (2018)

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DOI: 10.1109/ISCAS.2018.8350915

access: closed

type: Conference or Workshop Paper

metadata version: 2018-10-24

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  dblp key:
  - conf/iscas/AbediKEMH18
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  - https://dblp.org/rec/conf/iscas/AbediKEMH18
Razieh Abedi, Rouzbeh Kananizadeh, Amir Esmaili, Omeed Momeni, Payam Heydari:
A 53-61GHz Low-Power PLL With Harmonic Positive Feedback VCO in 65nm CMOS. ISCAS 2018: 1-5

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