"Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs."

Asit K. Mishra et al. (2011)

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DOI: 10.1145/2000064.2000074

access: closed

type: Conference or Workshop Paper

metadata version: 2025-02-07

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Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das:
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA 2011: 69-80

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