BibTeX record conf/isca/ChengZSIJL016

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@inproceedings{DBLP:conf/isca/ChengZSIJL016,
  author    = {Hsiang{-}Yun Cheng and
               Jishen Zhao and
               Jack Sampson and
               Mary Jane Irwin and
               Aamer Jaleel and
               Yu Lu and
               Yuan Xie},
  title     = {{LAP:} Loop-Block Aware Inclusion Properties for Energy-Efficient
               Asymmetric Last Level Caches},
  booktitle = {43rd {ACM/IEEE} Annual International Symposium on Computer Architecture,
               {ISCA} 2016, Seoul, South Korea, June 18-22, 2016},
  pages     = {103--114},
  publisher = {{IEEE} Computer Society},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISCA.2016.19},
  doi       = {10.1109/ISCA.2016.19},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/isca/ChengZSIJL016.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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