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"A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High ..."

Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal (2019)

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DOI: 10.1007/978-3-030-29516-5_20

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-27

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Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems. IntelliSys (1) 2019: 266-275

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