"Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling ..."

Hang-Ting Lue et al. (2024)

> Home

Details and statistics

DOI: 10.1109/IMW59701.2024.10536947

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-10

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/imw2/LueCLWL24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/imw2/LueCLWL24
Hang-Ting Lue, Wei-Chen Chen, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F² DRAM Below Equivalent 10nm Node. IMW 2024: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.