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"Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two ..."
Wei-Chen Chen et al. (2024)
- Wei-Chen Chen, Hang-Ting Lue, Ming-Hung Wu, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection. IMW 2024: 1-4
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