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"A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage ..."

Guoqing Wang et al. (2023)

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DOI: 10.1109/ICTA60488.2023.10364305

access: closed

type: Conference or Workshop Paper

metadata version: 2024-01-17

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Guoqing Wang, Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Jian Liu, Nanjian Wu, Liyuan Liu:
A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process. ICTA 2023: 120-121

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