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ORCID"FPGA Implementation of High Speed VLSI Architectures for AES Algorithm."
R. V. Kshirsagar, M. V. Vyawahare (2012)
- R. V. Kshirsagar, M. V. Vyawahare:
FPGA Implementation of High Speed VLSI Architectures for AES Algorithm. ICETET 2012: 239-242
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