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"FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time ..."

Raouf Senhadji-Navarro et al. (2007)

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DOI: 10.1109/ICECS.2007.4510959

access: closed

type: Conference or Workshop Paper

metadata version: 2020-06-04

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  dblp key:
  - conf/icecsys/NavarroGJB07
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  - https://dblp.org/rec/conf/icecsys/NavarroGJB07
Raouf Senhadji-Navarro, Ignacio Garcia-Vargas, Gabriel Jiménez-Moreno, Antón Civit Balcells:
FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration. ICECS 2007: 178-181

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