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"A 4Gb/s CMOS fully-differential analog dual delay-locked loop clock/data ..."
Zhiwei Mao, T. H. Szymansli (2003)
- Zhiwei Mao, T. H. Szymansli:
A 4Gb/s CMOS fully-differential analog dual delay-locked loop clock/data recovery circuit. ICECS 2003: 559-562
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