"A 4Gb/s CMOS fully-differential analog dual delay-locked loop clock/data ..."

Zhiwei Mao, T. H. Szymansli (2003)

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DOI: 10.1109/ICECS.2003.1301846

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Zhiwei Mao, T. H. Szymansli:
A 4Gb/s CMOS fully-differential analog dual delay-locked loop clock/data recovery circuit. ICECS 2003: 559-562

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