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"Design of a High Speed, Low Latency and Low Power Consumption DRAM Using ..."

Amin Chegeni, Khayrollah Hadidi, Abdollah Khoei (2007)

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DOI: 10.1109/ICECS.2007.4511203

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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Amin Chegeni, Khayrollah Hadidi, Abdollah Khoei:
Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure. ICECS 2007: 1167-1170

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