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"Automatic circuit generation for sequential logic debug."

Helder H. Avelar, Paulo F. Butzen, Renato P. Ribas (2015)

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DOI: 10.1109/ICECS.2015.7440269

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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Helder H. Avelar, Paulo F. Butzen, Renato P. Ribas:
Automatic circuit generation for sequential logic debug. ICECS 2015: 141-144

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