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"Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan."

Ramesh C. Tekumalla, Premachandran R. Menon (1997)

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DOI: 10.1109/ICCD.1997.628934

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/iccd/TekumallaM97
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  persistent URL:
  - https://dblp.org/rec/conf/iccd/TekumallaM97
Ramesh C. Tekumalla, Premachandran R. Menon:
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. ICCD 1997: 648-653

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