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"A VLSI array architecture with dynamic frequency clocking."

N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar (1996)

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DOI: 10.1109/ICCD.1996.563547

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  persistent URL:
  - https://dblp.org/rec/conf/iccd/RanganathanVB96
N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar:
A VLSI array architecture with dynamic frequency clocking. ICCD 1996: 137-140

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