"Design of Arithmetic Logic Unit Using Hybrid Power Reduction Methodologies ..."

S. Sasikala et al. (2023)

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DOI: 10.1109/ICCCNT56998.2023.10307664

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type: Conference or Workshop Paper

metadata version: 2023-11-30

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S. Sasikala, Balambigai Subramanian, P. Sivaranjani, V. Udhayasuriyan:
Design of Arithmetic Logic Unit Using Hybrid Power Reduction Methodologies For Super Computer Applications. ICCCNT 2023: 1-8

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