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"High Performance Circuit Techniques for Nueral Front-End Design in 65nm CMOS."

Rajasekhar Nagulapalli et al. (2018)

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DOI: 10.1109/ICCCNT.2018.8493806

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-25

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  dblp key:
  - conf/icccnt/NagulapalliHBZY18a
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  - https://dblp.org/rec/conf/icccnt/NagulapalliHBZY18a
Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Saddam Zourob, Nabil Yassine, B. Naresh Kumar Reddy:
High Performance Circuit Techniques for Nueral Front-End Design in 65nm CMOS. ICCCNT 2018: 1-4

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