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"Methodology for low power test pattern generation using activity threshold ..."

Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji (2007)

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DOI: 10.1109/ICCAD.2007.4397318

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/iccad/RaviDP07
Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji:
Methodology for low power test pattern generation using activity threshold control logic. ICCAD 2007: 526-529

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