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"An iterative area/performance trade-off algorithm for LUT-based FPGA ..."

Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen (1996)

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DOI: 10.1109/ICCAD.1996.568903

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/iccad/HuangJS96
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  persistent URL:
  - https://dblp.org/rec/conf/iccad/HuangJS96
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD 1996: 13-17

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