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"Parallel programming of a symmetric transport-triggered architecture with ..."

Blaine Rister et al. (2014)

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DOI: 10.1109/ICASSP.2014.6855236

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-29

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Blaine Rister, Pekka Jääskeläinen, Olli Silvén, Jari Hannuksela, Joseph R. Cavallaro:
Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding. ICASSP 2014: 8380-8384

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