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"Adder-based digital signal processor architecture for 80 NS cycle time."

Alois Rainer, Walter Ulbrich, Lajos Gazsi (1984)

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DOI: 10.1109/ICASSP.1984.1172308

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-07

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Alois Rainer, Walter Ulbrich, Lajos Gazsi:
Adder-based digital signal processor architecture for 80 NS cycle time. ICASSP 1984: 692-695

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